Power Efficient Design of DisplayPort (7.0) Using Low-voltage differential signaling IO Standard Via UltraScale Field Programming Gate Arrays

摘要

The DisplayPort (7.0) provides transection of serial-digital video displays, it has TX and RX Controllers along with pixel video interface, with streaming line rate of maximum 5.4 Gb/s. However, the limitation of DisplayPort (7.0) are detected in terms of power consumption. It has been reported that DisplayPort (7.0) consumes a massive power as it works on high frequency 1.62 GHz for high resolution video processing using HDMI Port. It is also stated that at full brightness the DisplayPort (7.0) consumes 49.0 W Therefore for power efficient DisplayPort (7.0) the full brightness power of DisplayPort (7.0) need be reduced. In this paper, a power efficient design for DisplayPort (7.0) is proposed using LVDS IO Standard. The proposed design is tested for different frequencies; 500 MHz, 700 MHz, 1.0 GHz, and 1.6 GHz. The design is implemented using vhdl in UltraScale FPGA. It is determined the designed vhdl based design of DisplayPort (7.0) can reduced 92% using LVDS IO Standard for all frequencies; 500 MHz, 700 MHz, 1.0 GHz, and 1.6 GHz, compared to vhdl based design of DisplayPort (7.0) without using IO Standard. The proposed design of vhdl based design of DisplayPort (7.0) using LVDS IO Standard offers no power consumption for DisplayPort (7.0) in standby mode. The vhdl based design of DisplayPort (7.0) using LVDS IO Standard will be helpful to process the high resolution video at low power consumption.